1. Field of the Invention
The present invention relates to a multi-valued logical circuit, and particularly to a multi-valued logical circuit which outputs one of a plurality of power supply potentials and a reference potential to an output node in response to a plurality of input signals.
2. Description of the Background Art
A multi-valued logical gate which outputs a logical level other than xe2x80x9cHxe2x80x9d and xe2x80x9cLxe2x80x9d levels in addition to a binary logical circuit which outputs an xe2x80x9cHxe2x80x9d or xe2x80x9cLxe2x80x9d level is conventionally mounted on a semiconductor integrated circuit.
FIG. 10 is a circuit diagram which shows a conventional three-valued inverter. In FIG. 10, this three-valued inverter includes P-channel MOS transistors 31 and 32 and an N-channel MOS transistor 33. P-channel MOS transistor 31 is connected between the line of a first power supply potential VDD (e.g., 3.0V) and an output node N31 and the gate thereof receives a signal VA. P-channel MOS transistor 32 is connected between the line of a second power supply potential VDDxe2x80x2 (e.g., 3.5V) and output node N31 and the gate thereof receives a signal VB. N-channel MOS transistor 33 is connected between output node N31 and the line of a ground potential VSS (0V) and the gate thereof receives a signal VC. The back gates of P-channel MOS transistors 31 and 32 are both connected to the line of second power supply potential VDDxe2x80x2.
FIG. 11 is a view which shows the operation of the three-valued inverter shown in FIG. 10. In FIG. 11, in a state 1, the potentials of signals VA, VB and VC are set at ground potential VSS, second power supply potential VDDxe2x80x2 and ground potential VSS, respectively. As a result, P-channel MOS transistor 31 becomes conductive, P-channel MOS transistor 32 and N-channel MOS transistor 33 become nonconductive and the potential of an output signal VO becomes first power supply potential VDD.
In a state 2, the potentials of signals VA, VB and VC are set at second power supply potential VDDxe2x80x2, ground potential VSS and ground potential VSS, respectively. As a result, P-channel MOS transistor 32 becomes conductive, P-channel MOS transistor 31 and N-channel MOS transistor 33 become nonconductive and the potential of output signal VO becomes second power supply potential VDDxe2x80x2.
In a state 3, the potentials of signals VA, VB and VC are all set at second power supply potential VDDxe2x80x2. As a result, P-channel MOS transistors 31 and 32 become nonconductive, N-channel MOS transistor 33 becomes conductive and the potential of output signal VO becomes ground potential VSS. It is noted that the same result can be obtained even if the potentials of signals VA and VB are both set at second power supply potential VDDxe2x80x2 and the potential of signal VC is set at first power supply potential VDD. As can be seen, this three-valued inverter can selectively output one of the three logical levels of first power supply potential VDD, second power supply potential VDDxe2x80x2 and ground potential VSS.
FIG. 12 is a circuit diagram which shows the configuration of another conventional three-valued inverter. Referring to FIG. 12, this three-valued inverter differs from that shown in FIG. 10 in that P-channel MOS transistor 31 is replaced by an N-channel MOS transistor 34. That is, N-channel MOS transistor 34 is connected between the line of first power supply potential VDD and output node N31 and the gate thereof receives signal VA.
FIG. 13 is a view which shows the operation of the three-valued inverter shown in FIG. 12. In FIG. 13, in state 1, the potentials of signals VA, VB and VC are set at second power supply potential VDDxe2x80x2, second power supply potential VDDxe2x80x2 and ground potential VSS, respectively. As a result, N-channel MOS transistor 34 becomes conductive, P-channel MOS transistor 32 and N-channel MOS transistor 33 become nonconductive and the potential of output signal VO becomes first power supply potential VDD.
In state 2, the potentials of signals VA, VB and VC are all set at ground potential VSS. As a result, P-channel MOS transistor 32 becomes conductive, N-channel MOS transistors 34 and 33 become nonconductive and the potential of output signal VO becomes second power supply potential VDDxe2x80x2.
In state 3, the potentials of signals VA, VB and VC are set at ground potential VSS, second power supply potential VDDxe2x80x2 and second power supply potential VDDxe2x80x2, respectively. As a result, N-channel MOS transistor 33 becomes conductive, N-channel MOS transistor 34 and P-channel MOS transistor 32 become nonconductive and the potential of output signal VO becomes ground potential VSS. It is noted that the same result can be obtained even if the potentials of signals VA, VB and VC are set at ground potential VSS, second power supply potential VDDxe2x80x2 and first power supply potential VDD, respectively.
Meanwhile, in case of the three-valued inverter shown in FIG. 10, not first power supply potential VDD but second power supply potential VDDxe2x80x2 is applied to the back gate of P-channel MOS transistor 31 for the following reason. If first power supply potential VDD is applied to the back gate of P-channel MOS transistor 31, the potential of the drain of P-channel MOS transistor 31 becomes second power supply potential VDDxe2x80x2, the PN junction between the drain and the back gate of P-channel MOS transistor 31 is directed in a forward direction and high current is carried to thereby cause latch-up in state 2 shown in FIG. 11. It is noted that P-channel MOS transistor 31 is constituted, as shown in FIG. 14, so that a gate electrode 31g is formed on the surface of an N type substrate 35 through a gate insulating film 31i and a P type source region 31s and a P type drain region 31d are formed on one side and the other side of gate electrode 31g, respectively. Gate electrode 31g, source region 31s, drain region 31d and N type substrate 35 become the gate, source, drain and back gate of P-channel MOS transistor 31, respectively.
In the three-valued inverter shown in FIG. 10, however, different power supply potentials VDD and VDDxe2x80x2 are applied to the source and the back gate of P-channel MOS transistor 31, respectively. Due to this,if power supply potentials VDD and VDDxe2x80x2 become VDD greater than VDDxe2x80x2 in a transient period before power supply potentials VDD and VDDxe2x80x2 reach normal potentials during a power-up period or the like, the PN junction between the source and the back gate of P-channel MOS transistor 31 is directed in the forward direction and latch-up may possibly occur.
On the other hand, in the three-valued inverter shown in FIG. 12, since P-channel MOS transistor 31 is replaced by N-channel MOS transistor 34, latch-up does not occur during a power-up period described above. However, in state 1 shown in FIG. 13, the potential of the drain of N-channel MOS transistor 31 becomes first power supply potential VDD=3V, the potential of the gate thereof becomes second power supply potential VDDxe2x80x2=3.5V and N-channel MOS transistor 34 is source-follower connected. Due to this, the potential of the source of N-channel MOS transistor 34, i.e., the potential of output signal VO cannot be higher than a potential VDDxe2x80x2=Vth obtained by subtracting the threshold voltage Vth of N-channel MOS transistor 34 from gate potential VDDxe2x80x2 of N-channel MOS transistor 34. If threshold voltage Vth is, for example, not higher than 0.5V, the potential of output signal VO becomes VO=VDD=3V. However, if threshold voltage Vth is higher than 0.5V, the potential of output signal VO becomes VO=VDDxe2x80x2xe2x88x92Vth less than VDD=3V, i.e., lower than VDD.
It is, therefore, the main object of the present invention to provide a multi-valued logical circuit wherein no latch-up occurs and an output potential is not lowered by as much as the threshold voltage of a transistor.
A multi-valued logical circuit according to this invention includes: a first transistor of a first conductive type provided to correspond to each power supply potential, having both a first electrode and a substrate electrode receiving the corresponding power supply potential, and becoming conductive in response to input of the corresponding signal; a second transistor of the first conductive type provided to correspond to each power supply potential, having a first electrode connected to a second electrode of the first transistor, having both a second electrode and a substrate electrode connected to the output node, and becoming conductive in response to the input of the corresponding signal; and a third transistor of a second conductive type having a first electrode connected to the output node, having a second electrode receiving the reference potential, and becoming conductive in response to the input of the Nth signal. Since the first electrode and the substrate electrode of the first transistor are both connected to the corresponding power supply potential line, no latch-up occurs during a power-up period or the like. In addition, the first and second transistors are connected in series. Due to this, even if the potential of the output node differs from the corresponding power supply potential, the node between the first and second transistors turns into a floating state and no latch-up occurs. Further, since only the transistors of the first conductive type are used for outputting power supply potentials, an output potential is not lowered by as much as the threshold voltage of the transistor of the second conductive type.
In addition, another multi-valued logical circuit according to this invention includes: a first switching circuit provided to correspond to each power supply potential, and applying the corresponding power supply potential to the output node in response to input of at least one first signal among a plurality of first signals included in the corresponding signal group; and a second switching circuit applying the reference potential to the output node in response to the input of all plurality of second signals included in the Nth signal group. The first switching circuit includes: a first transistor of a first conductive type provided to correspond to each first signal included in the corresponding signal group, having both a first electrode and a substrate electrode receiving the corresponding power supply potential, and becoming conductive in response to the input of the corresponding first signal; and a second transistor of the first conductive type provided to correspond to each first signal included in the corresponding signal group, having a first electrode connected to a second electrode of the first transistor, having a second electrode and a substrate electrode both connected to the output node, and each becoming conductive in response to the input of the corresponding first signal. The second switching circuit includes a plurality of third transistors of a second conductive type connected in series between the output node and a line of the reference potential, becoming conductive in response to the input of the plurality of second signals included in the Nth signal group, respectively. In this case, it is possible to constitute a multi-valued NAND gate to which no latch-up occurs and the output potential of which is not lowered by as much as the threshold voltage of the transistor.
Furthermore, yet another multi-valued logical circuit according to this invention includes: a first switching circuit provided to correspond to each power supply potential, and applying the corresponding power supply potential to the output node in response to input of all a plurality of first signals included in the corresponding signal group; and a second switching circuit applying the reference potential to the output node in response to the input of at least one second signal among a plurality of second signals included in the Nth signal group. The first switching circuit includes: a first transistor of a first conductive type having a first electrode and a substrate electrode both connected to the output node, and becoming conductive in response to the input of at least one signal among the plurality of first signals included in the corresponding signal group; and a plurality of second transistors of the first conductive type connected in series between a second electrode of the first transistor and a line of the corresponding potential, and becoming conductive in response to the input of the plurality of first signals respectively. The second switching circuit includes a plurality of third transistors of a second conductive type connected in parallel between the output node and a line of the reference potential, and becoming conductive in response to the input of the plurality of second signals respectively. In this case, it is possible to constitute a multi-valued NOR gate to which no latch-up occur and the output potential of which is not lowered by as much as the threshold voltage of the transistor.